1. Field of the Invention
The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to a fin device with a blocking layer in the channel region.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors, or complementary MOSFET transistors or CMOS) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices (at 20 nm or earlier CMOS nodes) or three-dimensional (3D) devices, such as finFET devices (at 20 nm or later 14 nm CMOS nodes).
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D finFET device, typically includes doped source/drain regions that are formed in a semiconductor substrate that are separated by a channel region. A gate insulation layer (e.g., dielectric) is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure or gate stack for the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. In a planar FET device, the gate structure is formed above a substantially planar upper surface of the substrate. The gate structures for such planar FET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region (leading to large leakage current between source and drain in “off-state”) and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar MOSFET, a so-called finFET device has a three-dimensional (3D) structure. FIG. 1 is a side view of an illustrative prior art finFET semiconductor device 100 that is formed above a semiconductor substrate 105. In this example, the finFET device 100 includes three illustrative fins 110, a gate structure 115, sidewall spacers 120 and a gate cap 125. The gate structure 115 is typically made up of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material on a thin silicon dioxide interfacial layer, and one or more conductive material layers (e.g., metal, metal-nitride and/or polysilicon) that serve as the work-function material and gate electrode for the device 100. The fins 110 have a three-dimensional configuration. The portions of the fins 110 covered by the gate structure 115 define the channel region of the finFET device 100. An isolation structure 130 is formed between the fins 110, similar to the shallow trench isolation (STI) structure formed between planar transistors.
In a finFET device 100 formed above a bulk substrate, parasitic source and drain capacitances and resulting source-to-drain leakage are performance-limiting factors, similar to planar CMOS devices. To reduce source-to-drain leakage, a counter-doped implant region (i.e., using the opposite type of dopants as the source and drain), commonly referred to as a punch through stopper implant, may be provided in the lower portion of the channel region of the fin. This counter-doping of the fin reduces carrier mobility and damages to the fin due to the implantation through the fin regions. Even with a counter-doped region, the junction leakage from the source and drain to the substrate still significantly contributes to total device leakage at off-state.
Another approach involves locally implanting ions, such as oxygen, in the channel region during the gate replacement process after the sacrificial polysilicon is removed and prior to forming the replacement gate material. However, this localized oxygen ion implant often creates unbalanced strain in the device.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.